Field
The present disclosure relates generally to a standard cell architecture, and more particularly, to a metal oxide semiconductor (MOS) integrated circuit (IC) standard cell architecture for a filler cell that reduces leakage current and improves decoupling capacitance.
Background
Standard cells of an IC implement digital logic. An application-specific IC (ASIC), such as a system-on-a-chip (SoC) device, may contain thousands to millions of standard cells. A typical MOS IC device includes a stack of sequentially formed layers. Each layer may be stacked or overlaid on a prior layer and patterned to form the shapes that define transistors (e.g., field effect transistors (FETs) and/or a fin-shaped FET (FinFET)) and connect the transistors into circuits.
As MOS IC devices are fabricated at smaller sizes, manufacturers are finding it more difficult to integrate larger numbers of standard cell devices on a single chip. If every cell in a MOS IC device is used for a logic function and requires inter-cell routing (e.g., 100% utilization), there may not be enough space for required inter-cell routing between the standard cells. In order to reduce utilization in a MOS IC device, engineering change order (ECO) cells, decoupling capacitor cells, and filler cells may be used. A utilization of around 70%-80% may provide enough space to allow for the requisite inter-cell routing between standard cells. Typically, a majority of the 20%-30% of non-utilization may be obtained through the use of filler cells, as filler cells have less current leakage than decoupling capacitor cells and provide some decoupling capacitance. Filler cells (e.g., rather than empty cells without any transistor patterning) may be necessary when the power rails and/or n-doped wells are formed continuous across the MOS IC device. An IC simulator may be inaccurate with estimating leakage of filler cells. There is currently a need for a filler cell that improves a leak current estimation in an IC simulator. Further, there is currently a need to reduce the leakage current of filler cells without significantly reducing the decoupling capacitance of filler cells.